1. Field of the Invention
This invention relates to a semiconductor device having a gate and source-and-drain regions, and a method of fabricating thereof, which are particularly preferable when applied to a CMOS transistor.
2. Description of the Related Art
Conventional CMOS transistors generally employ a polysilicon gate electrode doped with an n-type impurity for the n-channel MOS transistor (nMOS transistor) composing thereof. This is because the threshold voltage can readily be controlled to desired values. The nMOS transistor is turned ON when applied with a positive voltage through the gate electrode, which causes bending of the energy band of polysilicon, and generates a depletion layer within the gate electrode in the vicinity of the interface with a gate insulating film. Such production of the depletion layer undesirably lowers the gate capacitance and thus reduces ON current. To suppress the lowering of the gate capacitance, it is necessary to raise concentration of the n-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film.
The same will apply to the p-channel MOS transistor (pMOS transistor) which employs a polysilicon gate electrode doped with a p-type impurity, where it is also necessary to raise concentration of the p-type impurity within the gate electrode in the vicinity of the interface with the gate insulating film in order to suppress lowering of the gate capacitance during the ON status.
In a general procedure for fabricating the aforementioned nMOS and pMOS transistors, the source-and-drain regions are formed by ion implantation, where the gate electrodes which serve as masks are also concomitantly doped.
To suppress lowering in the gate capacitance, it is necessary to suppress formation of the depletion layer within the gate electrode, and it is thus necessary to raise the dose of the impurity introduced into the gate electrode, which impurity is concomitantly doped also into the source-and-drain regions. This successfully raises the impurity concentration within the gate electrode, but also raises the impurity concentration in the source-and-drain regions, which undesirably promotes lateral diffusion of the impurity in the source-and-drain regions, and results in degradation of short-channel resistance.
One known solution for addressing the problem relates to reduction in height of the gate electrode, which can substantially increase the impurity concentration even if the dose of impurity introduced to the gate electrode remains unchanged. This solution, however, raises another problem that too low height of the gate electrode may result in punch-through of the impurity introduced into the gate electrode into the channel, which undesirably varies the threshold voltage. The technique for reducing the height of gate electrode is thus limitative.